1. Field of the Invention
The present invention relates to a method for manufacturing a multilevel interconnection structure. In particular, the present invention relates to a method for forming a multilevel interconnection structure on a wafer which is capable of preventing peeling-off of the deposited films in the peripheral area and an intermediate area of the wafer during subsequent fabrication steps.
2. Description of the Prior Art
Because of the demand for finer patterned, higher density semiconductor devices, the semiconductor devices include fine-patterned, multilevel interconnection structures in the semiconductor devices.
In order to form fine-patterned, multilayer interconnections, an embedded multilevel interconnection structure has been frequently employed for interconnections of circuit elements in the semiconductor devices. Such embedded multilevel interconnection structures are formed by a damascene process using the technique of chemical mechanical polishing (CMP) method.
Referring now to FIGS. 1A to 1K, a conventional method of forming the embedded multilevel interconnection structure using the damascene process will be described. These figures show partial sectional views of a central area of a wafer, which is used for forming the product chips, during consecutive steps of fabrication process therefor. In the descriptions to follow, the film thickness, width and other dimensions or values are mere examples, and the present invention is not limited to those values in any sense.
First, as shown in FIG. 1A, a first multilayer interlevel dielectric film 14 composed of a 4000-xc3x85-thick SiO2 film(top layer)/a 500-xc3x85-thick SiON film(bottom layer) to be used for forming trenches therein is deposited on a wafer, or a substrate 12.
Then, a photoresist film is formed on the dielectric film 14 by a coating process, followed by a photolithographic process to form an etching mask 16 having an interconnection trench pattern thereon, as shown in FIG. 1B.
Next as shown in FIG. 1C, first interconnection trenches 18 are formed by etching the dielectric film 14 by the etching mask 16.
After removing the etching mask 16, a barrier layer composed of a 200-xc3x85-thick TaN layer (bottom layer)/a 200-xc3x85-thick Ta layer (top layer) and a 1000-xc3x85-thick copper layer are formed in this order on the dielectric film 14 by using a barrier-seed sputtering method. On top of those films, a 6000-xc3x85-thick copper (Cu) layer is formed by Cu plating to fill the interconnection trenches 18. In FIG. 1D, such multilayer metallic film is denoted by numeral 20, which is herein called a Cu layer 20.
Next, the Cu layer 20 is polished by the CMP method to form first level interconnections 22 that are mostly made of Cu filling the interconnection trenches 18 formed in the dielectric film 14.
In the next step, as shown in FIG. 1F, on the dielectric film 14 having trenches 18 receiving therein the exposed first level interconnections 22, a first interlevel dielectric film 24 is formed that is composed of a 500-xc3x85-thick SiN film (bottom layer)/a 7000-xc3x85-thick SiO2 film (top layer).
Subsequently, as shown in FIG. 1G, an etching mask (not shown) is formed on the first interlevel dielectric film 24. Then, the interlevel dielectric film 24 underlying the etching mask is etched to form 0.2-xcexcm-diameter via holes 26 which expose the first level interconnection 22 therethrough.
Next, a 4000-xc3x85-thick tungsten (W) layer is deposited by CVD (Chemical Vapor Deposition) method on the first interlevel dielectric film 24 while filling the via holes 26. Then, the tungsten layer formed on top of the first interlevel dielectric film 24 is removed by a CMP process to leave first tungsten plugs 28 that contact with the respective first level interconnections 22, as shown in FIG. 1H.
In the next step, by the process steps similar to those employed in forming the first level interconnections 22, a second multilayer dielectric film 30 to be used for forming trenches therein is deposited on the interlevel dielectric film 24 as well as the exposed first tungsten plugs 28; the dielectric film 30 is patterned to form interconnection trenches; a Cu layer is deposited; and as shown in FIG. 1I, second level interconnections 32 are formed by a CMP process.
In the following steps, another interlevel dielectric film 34 having a structure similar to the structure of the interlevel dielectric film 24 is deposited on the second level interconnections 32 and the second dielectric film 30; via holes are formed by using the process similar to that used in forming the first tungsten plugs 28; and as shown in FIG. 1J, second tungsten plugs 36 are formed that connect to the second level interconnections 32.
By using the above process steps, the first level interconnections 22 and second level interconnections 32 which are called herein lower-level interconnections are fabricated.
Next, as shown in FIG. 1K, a third interlevel dielectric film 38 to be used for forming trenches and composed of a 1000-xc3x85-thick SiON film (bottom layer)/a 19000-xc3x85-thick SiO2 film (top layer) is formed on the interlevel dielectric film 34 as well as the exposed second tungsten plugs 36.
Subsequently, interconnection trenches are formed by patterning the dielectric film 38, and a barrier layer composed of a 200-xc3x85-thick TaN layer (bottom layer)/a 200-xc3x85-thick Ta layer (top layer) and a 2000-xc3x85-thick Cu film are formed in this order. On those layers, a 30000-xc3x85-thick Cu plating layer is formed by a plating technique. Next, a third level interconnection 40 composed of multilayer metallic films is formed by CMP processing of the Cu plating layer, as shown in FIG. 1K.
In the following step, on the interconnection 40, a multilayer interlevel dielectric film 42 composed of a 500-xc3x85-thick SiN film (bottom layer)/a 7000-xc3x85-thick SiO2 film (top layer) is formed and then via holes of 0.56-xcexcm-diameter are formed in the dielectric film 42. Further, a 4000-xc3x85-thick tungsten film is deposited by CVD method and third tungsten plugs 44 are formed by CMP processing of the tungsten film as shown in FIG. 1L.
Next a fourth interlevel dielectric film 46 to be used for forming trenches therein is deposited and patterned to form interconnection trenches. Then fourth level interconnections 48 connecting to the tungsten plugs 44 are formed in the steps similar to those used in forming the third level interconnections 40, as shown in FIG. 1L.
By the above process steps, the third-level interconnections 40 and the fourth level interconnections 48 are formed and are referred to as upper level interconnections hereinafter.
In the conventional damascene process, there are some drawbacks wherein the tungsten particles generated by the CMP process cause some problems such as peeling-off of the deposited films in the subsequent steps.
It is therefore an object of the present invention to provide a method for forming a multilevel interconnection structure in a semiconductor device by using a damascene process wherein peeling-off of the films is suppressed.
The present invention provides a method for manufacturing on a wafer a plurality of semiconductor chips each having a multilevel interconnection structure by using a damascene technique, the method comprising the steps of: separating the wafer into three areas including a peripheral area, an intermediate area and a central area, the central area including a plurality of product chips; forming a first dielectric film overlying the wafer, the first dielectric film having therein first trenches in the intermediate area and the central area; forming lower-level interconnections in the first trenches by using deposition and CMP processes; forming a second dielectric film overlying the first dielectric film and the lower-level interconnections, the second dielectric film having second trenches in the central area; forming upper-level interconnections in the second trenches by using deposition and CMP processes; and wet-etching remaining films in the peripheral area after the CMP process for the upper-level interconnections.
In accordance with the method of the present invention, the wet etching for the remaining films in the peripheral area does not affect the structure in the product chips formed in the central area of the wafer due to provision of the intermediate area. dr
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.
FIGS. 1A-1L are sectional views of the periphery of the wafer, consecutively showing the process steps of forming multilevel interconnection structure in the central area of the wafer;
FIG. 2 is a schematic perspective view illustrating the periphery of the wafer where a Cu layer is formed on the rear side beyond the periphery;
FIGS. 3A-3C are sectional views illustrating the defect generated in the conventional method for forming a multilevel interconnection structure;
FIG. 4 is a top plan view of a quarter of the wafer for showing the separated areas;
FIGS. 5A-5R are sectional views of a semiconductor chip arranged in a peripheral area of the wafer, consecutively showing the process steps in a method according to a preferred embodiment of the present invention; and
FIGS. 6A and 6B are schematic sectional views, consecutively showing the process steps in a method according to another embodiment of the present invention.